Advanced Single-stage Pfc Techniques with Voltage- Doubler Rectifier Front End for Universal-line Applications

line (90-265 Vac) applications with a hold-up time requirement. As shown in Chapter 5, the difficulty of these SPFC circuits to deal with a wide line range and long hold-up time requirement stems from the fact that the voltage of the energy-storage capacitor, VB, varies with the line voltage and load current. In most applications, with a proper design, VB(max) can be kept in the 400-420 Vdc range, which warrants a use of a 450-V electrolytic capacitor. Since the value of CB is determined from the hold-up time requirement at the minimum line (worst case), the SPFC approach requires a relatively bulky and expensive energy-storage capacitor with VB in 120-140 Vdc range at 90Vac input and full load condition. Moreover, due to a wide-range variation of VB that is the input to the dc/dc stage, the conversion efficiency of the dc/dc stage is reduced. In contrast, the two-stage approach, in which VB is independently regulated at approximately 380 Vdc, requires a much smaller and, therefore, cheaper electrolytic capacitor